This application claims the priority of Korean Patent Application No. 2002-79633 filed on Dec. 13, 2002, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference.
1. Field of the Invention
The present invention relates to a data latch circuit and a method for improving operating speed in data latch circuits.
2. Description of the Related Art
Techniques of reducing the number of logic gate devices of a combinational logic block and techniques related to changing circuit style have been investigated in an effort to develop high-speed highly-integrated circuits such as microprocessor. A combinational logic block may refer to logic circuits that include logic gate devices such as AND gates and OR gates. Reducing the number of logic gate devices in a given logic circuit also reduced the number of devices through which input data must pass, potentially improving circuit operating speed. As an example of changing circuit style, static circuits may be replaced by dynamic circuits. In general, the operating speed of a dynamic circuit is higher than that of the static circuit.
In latch circuits, which store and output data, there are several techniques for reducing a delay time called “clock to q,”. The clock to q delay time represents a time delay from the moment data is input to the latch circuit to the moment the data is output from the latch circuit. Until now, reducing the number of logic gate devices of a combinational logic block or changing a static circuit into a dynamic circuit have been considered effective ways of reducing the clock to q delay time.
FIG. 1 is a diagram of a conventional data latch circuit. The conventional data latch circuit 100 includes an inverter 120 which inverts a clock signal CLK, and a latch 110 which is activated in response to an inverted signal of the clock signal CLK. Latch 110 receives, and outputs, an enabling signal (ENS). A logical multiplier 130 calculates a logical multiplication of the output from latch 110 and the CLK to generate a gated clock signal (GCLK). A sense amplifier 140 receives, and transmits, input data, (referred to hereafter as ‘INDATA’) in response to the GCLK. A cascode logic unit 150 stores the output of the sense amplifier 140 and generates output data (referred to hereafter as ‘OUTDATA’). The latch 110 and the logical multiplier 130 are used to generate the GCLK, which is produced from the logical multiplication of the CLK and the ENS. The data latch circuit 100 may perform the same function as a flip-flop circuit, for example.
FIG. 2 is a timing diagram illustrating operations of the conventional data latch circuit of FIG. 1. The ENS is input first at a high logic level (before the CLK is input) and then the CLK is input at a high logic level. With both CLK and ENS at a logic level high, the latch 110 is activated in response to an inverted signal of the CLK. Since both input signals of logical multiplier 130 are at a high logic level, the logical multiplier 130 outputs the GCLK at a high logic level.
In FIG. 2, reference element “A” represents a delay time of the GCLK based on the CLK. The GCLK has the delay time of “A” in FIG. 2 due to the operations required of the latch 110 and the logical multiplier 130. When the INDATA is input to the sense amplifier 140, the sense amplifier 140 outputs (as the OUTDATA) the INDATA stored in the cascode logic unit 150. This stored INDATA is output in response to the GCLK.
In FIG. 2, reference element “B” represents a delay time between a time from which the INDATA is input to the sense amplifier 140, to a time at which, the OUTDATA is output in response to the GCLK. The INDATA has the delay time of “B” in FIG. 2 due to the sense amplifier 140 and the cascode logic unit 150. Accordingly, to synchronize the INDATA with the CLK and output the INDATA as OUTDATA, a delay time of “A+B”, (e.g., the clock to q delay time) is generated. This is undesirable in high-speed highly-integrated circuits such as microprocessors.